The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to dual-ported content addressable memories for a simultaneous operation flash memory.
Flash random access memory (RAM), more commonly known as flash memory, is a form of non-volatile storage that uses a memory cell design with a floating gate. High voltages are applied to the memory cell inputs to program or store charge on the floating gate or to erase or remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce a thin dielectric material, reducing the amount of electronic charge on the floating gate. Erasing a cell sets the logical value of the cell to xe2x80x9c1xe2x80x9d while programming the cell sets the logical value to xe2x80x9c0xe2x80x9d. Aside from programming or erasing operations, a flash memory operates similarly to a randomly accessible read only memory (ROM). Conventionally, a flash memory chip, including the flash memory storage cells and support logic/circuitry, is made by fabricating layers of semiconductor material and interconnect layers of polysilicon and first and second metal layers onto a substrate. It will be appreciated that there are numerous integrated circuit fabrication techniques, involving more or fewer layers, which are applicable herein.
Redundant core cell arrays are utilized to substitute for inoperative memory core cells of primary or regular arrays. Content addressable memory (CAM) circuitry may be utilized to assist in redundancy substitution. Redundancy CAM cells store information regarding the locations of inoperative memory cells so that redundant arrays of memory cells may be used to substitute for the inoperative memory cells of the primary arrays.
Typically, the arrays of memory cells are tested by the manufacturer for performance and accuracy prior to utilization by a customer or user. The redundancy CAM cells are erased and programmed with the locations of inoperative memory cells as appropriate following the testing stage.
Newer technologies, such as simultaneous read and write operation flash memories, present opportunities for the redesign of CAM circuitries and architectures to meet increasing standards of system performance, and device density. It would be desirable to implement a more efficient redundancy CAM circuitry and architecture in a flash memory.